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ADE7880
Data Sheet
Parameter 1 , 2
Min
Typ
Max
Unit
Test Conditions/Comments
WAVEFORM SAMPLING
Current and Voltage Channels
Sampling CLKIN/2048, 16.384 MHz/2048 =
8 kSPS
See the Waveform Sampling Mode
section
Signal-to-Noise Ratio, SNR
Signal-to-Noise-and-Distortion Ratio,
72
72
dB
dB
PGA = 1
PGA = 1
SINAD
Bandwidth (?3 dB)
TIME INTERVAL BETWEEN PHASES
3.3
kHz
Measurement Error
0.3
Degrees
Line frequency = 45 Hz to 65 Hz, HPF on
CF1, CF2, CF3 PULSE OUTPUTS
Maximum Output Frequency
Duty Cycle
68.818
50
kHz
%
WTHR = VARTHR = VATHR = 3
If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is even and > 1
(1 + 1/CFDEN) ×
50
%
If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is odd and > 1
Active Low Pulse Width
Jitter
80
0.04
ms
%
If CF1, CF2, or CF3 frequency < 6.25 Hz
For CF1, CF2, or CF3 frequency = 1 Hz and
nominal phase currents are larger than
10% of full scale
REFERENCE INPUT
REF IN/OUT Input Voltage Range
1.1
1.3
V
Minimum = 1.2 V ? 8%; maximum =
1.2 V + 8%
Input Capacitance
ON-CHIP REFERENCE
10
pF
Nominal 1.21 V at the REF IN/OUT pin at
T A = 25°C
PSM0 and PSM1 Modes
Reference Error
Output Impedance
1
±2
mV
kΩ
Temperature Coefficient
CLKIN
10
50
ppm/°C
All specifications CLKIN of 16.384 MHz
Input Clock Frequency
16.22
16.384
16.55
MHz
Crystal Equivalent Series Resistance
CLKIN Load Capacitor 4
CLKOUT Load Capacitor 4
30
20
20
200
40
40
Ω
pF
pF
LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS,
RESET, PM0, AND PM1
Input High Voltage, V INH
Input Current, I IN
Input Low Voltage, V INL
Input Current, I IN
Input Capacitance, C IN
LOGIC OUTPUTS—IRQ0, IRQ1, AND
2.4
82
0.8
?7.3
10
V
nA
V
μA
pF
VDD = 3.3 V ± 10%
Input = VDD = 3.3 V
VDD = 3.3 V ± 10%
Input = 0, VDD = 3.3 V
VDD = 3.3 V ± 10%
MISO/HSD
Output High Voltage, V OH
I SOURCE
3.0
800
V
μA
VDD = 3.3 V ± 10%
Output Low Voltage, V OL
I SINK
0.4
2
V
mA
VDD = 3.3 V ± 10%
CF1, CF2, CF3/HSCLK
Output High Voltage, V OH
I SOURCE
2.4
500
V
μA
VDD = 3.3 V ± 10%
Output Low Voltage, V OL
I SINK
0.4
2
V
mA
VDD = 3.3 V ± 10%
Rev. A | Page 6 of 104
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